Input power monitoring circuit

ABSTRACT

An input power monitoring circuit includes a rectifier circuit, a divided voltage generator circuit, a divided voltage comparator circuit, a switching circuit, and a computing device. The divided voltage comparator circuit is configured in such a manner that polarity of an output signal that is outputted from a first comparator upon a first rectified divided voltage exceeding a first comparison voltage is opposite to polarity of an output signal that is outputted from a second comparator upon a second rectified divided voltage exceeding a second comparison voltage. Output terminals of the first and second comparators are connected to each other. A connection point between the output terminals of the first and second comparators is connected to an input terminal of the switching circuit. The computing device measures frequency of a pulse signal outputted from the switching circuit, and determines the voltage state of input power based on the measured frequency.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on Japanese Patent Application No. 2021-138799 filed with the Japan Patent Office on Aug. 27, 2021, the entire content of which is hereby incorporated by reference.

BACKGROUND 1. Technical Field

One aspect of the present disclosure relates to an input power monitoring circuit.

2. Related Art

JP-A-2007-322192 discloses an input voltage monitoring circuit that inputs alternating current power and monitors voltage. In the input voltage monitoring circuit, the voltage of a pulsating current that is generated from the rectified alternating current power is compared with a predetermined threshold voltage to form a pulse in relation to the voltage waveform of the alternating current power. Furthermore, the time width of the pulse is compared with a predetermined time width to monitor the voltage of the alternating current power.

SUMMARY

An input power monitoring circuit includes: a rectifier circuit configured to rectify periodic input power and generate a rectified voltage; a divided voltage generator circuit configured to divide the rectified voltage and generate a first rectified divided voltage and a second rectified divided voltage being a voltage lower than the first rectified divided voltage; a divided voltage comparator circuit including a first comparator configured to compare the first rectified divided voltage with a first comparison voltage, and a second comparator configured to compare the second rectified divided voltage with a second comparison voltage; a switching circuit configured to output a pulse signal in relation to a voltage state of the input power based on an output signal outputted from the first comparator, and an output signal outputted from the second comparator; and a computing device configured to determine the voltage state of the input power based on the pulse signal. The divided voltage comparator circuit is configured in such a manner that polarity of the output signal that is outputted from the first comparator upon the first rectified divided voltage exceeding the first comparison voltage is opposite to polarity of the output signal that is outputted from the second comparator upon the second rectified divided voltage exceeding the second comparison voltage. An output terminal of the first comparator and an output terminal of the second comparator are connected to each other in the divided voltage comparator circuit. A connection point between the output terminal of the first comparator and the output terminal of the second comparator is connected to an input terminal of the switching circuit. The computing device measures frequency of the pulse signal, and determines the voltage state of the input power based on the measured frequency.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates an input power monitoring circuit according to an embodiment of the present disclosure;

FIG. 2 illustrates the voltage waveform of a rectified divided voltage of when an input power voltage does not change, and the output waveform of a switching circuit;

FIG. 3 illustrates the voltage waveform of the rectified divided voltage of when the input power voltage drops, and the output waveform of the switching circuit;

FIG. 4 illustrates the voltage waveform of the rectified divided voltage of when the input power voltage drops further, and the output waveform of the switching circuit;

FIG. 5 illustrates the voltage waveform of the rectified divided voltage of when the input power voltage rises, and the output waveform of the switching circuit;

FIG. 6 illustrates the voltage waveform of the rectified divided voltage of when the input power voltage rises further, and the output waveform of the switching circuit; and

FIG. 7 is a flowchart illustrating a voltage determination process of a computing device.

DETAILED DESCRIPTION

In the following detailed description, for purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

In the case of a method for determining the voltage of alternating current power on the basis of the time width of a pulse as in JP-A-2007-322192, a change in pulse width caused by voltage distortion is large. Therefore, it is difficult to excellently determine the voltage of the alternating current power in some cases. Hence, there is room for further improvement in excellently monitoring an input power voltage.

One object of the present disclosure is to provide an input power monitoring circuit that can excellently determine a change in input power voltage.

An input power monitoring circuit according to one aspect of the present disclosure (the present input power monitoring circuit) includes: a rectifier circuit configured to rectify periodic input power and generate a rectified voltage; a divided voltage generator circuit configured to divide the rectified voltage and generate a first rectified divided voltage and a second rectified divided voltage being a voltage lower than the first rectified divided voltage; a divided voltage comparator circuit including a first comparator configured to compare the first rectified divided voltage with a first comparison voltage, and a second comparator configured to compare the second rectified divided voltage with a second comparison voltage; a switching circuit configured to output a pulse signal in relation to a voltage state of the input power based on an output signal outputted from the first comparator, and an output signal outputted from the second comparator; and a computing device configured to determine the voltage state of the input power based on the pulse signal. The divided voltage comparator circuit is configured in such a manner that polarity of the output signal that is outputted from the first comparator upon the first rectified divided voltage exceeding the first comparison voltage is opposite to polarity of the output signal that is outputted from the second comparator upon the second rectified divided voltage exceeding the second comparison voltage. An output terminal of the first comparator and an output terminal of the second comparator are connected to each other in the divided voltage comparator circuit. A connection point between the output terminal of the first comparator and the output terminal of the second comparator is connected to an input terminal of the switching circuit. The computing device measures frequency of the pulse signal, and determines the voltage state of the input power based on the measured frequency.

According to the input power monitoring circuit, it is possible to provide an input power monitoring circuit that can excellently determine a change in input power voltage.

An embodiment of the present disclosure is described hereinafter with reference to the drawings. Descriptions of members having the same reference numerals as members already described in the detailed description are omitted for the convenience of description. Moreover, the dimensions of each member illustrated in the drawings may be different from actual dimensions thereof for the convenience of description.

FIG. 1 illustrates an input power monitoring circuit according to the embodiment of the present disclosure. As illustrated in FIG. 1 , an input power monitoring circuit 1 includes a rectifier circuit 2, a divided voltage generator circuit 3, a divided voltage comparator circuit 4, a switching circuit 5, and a computing device 6. Moreover, the input power monitoring circuit 1 is provided with input terminals Vin1 and Vin2 to which the voltage of power to be monitored is inputted. For example, an alternating current voltage (AC 200 V, 60 Hz) of mains electric power is inputted into the input terminals Vin1 and Vin2. In the illustrated example, a case where the voltage of alternating current power is inputted is described. However, the power to be monitored is not limited to alternating current power. The voltage of power to be inputted is simply required to be a periodic voltage such as a sinusoidal wave.

The rectifier circuit 2 is configured as a full-wave bridge rectifier circuit including four diodes D1 to D4 as rectification elements. The input terminal Vin1 is connected to a terminal 21 of the rectifier circuit 2, and the input terminal Vin2 is connected to a terminal 23. The rectifier circuit 2 full wave rectifies the alternating current voltage of the alternating current power that has been inputted into the input terminals Vin1 and Vin2, to generate a rectified voltage P1 of a pulsating current.

The divided voltage generator circuit 3 divides the rectified voltage generated by the rectifier circuit 2, according to the resistance of resistors. In the illustrated example, the divided voltage generator circuit 3 includes four resistors, resistors 31 to 34. The resistors 31 to 34 are connected in series between terminals 22 and 24 of the rectifier circuit 2. A connection line between the resistor 34 and the terminal 24 is connected to a ground GND1. The resistance value of each of the resistors 31 to 34 is determined in such a manner that each of the voltage value of a connection point 35 between the resistors 32 and 33 and the voltage value of a connection point 36 between the resistors 33 and 34 becomes a predetermined voltage value set as the input voltage of the divided voltage comparator circuit 4.

The divided voltage generator circuit 3 divides the rectified voltage P1 generated by the rectifier circuit 2, according to the resistance of the resistors, to generate a first rectified divided voltage P2, and a second rectified divided voltage P3 being a voltage lower than the first rectified divided voltage P2. The first rectified divided voltage P2 is a rectified divided voltage outputted to the connection point 35. The second rectified divided voltage P3 is a rectified divided voltage outputted to the connection point 36.

The divided voltage comparator circuit 4 includes at least two comparators that function as comparators. Of the two comparators, a first comparator 41 includes an input terminal IN-A and an output terminal OUT-A. Moreover, a second comparator 42 includes an input terminal IN-B and an output terminal OUT-B. The first rectified divided voltage P2 outputted from the connection point 35 of the divided voltage generator circuit 3 is inputted into the input terminal IN-A of the first comparator 41. Moreover, the second rectified divided voltage P3 outputted from the connection point 36 of the divided voltage generator circuit 3 is inputted into the input terminal IN-B of the second comparator 42. The first comparator 41 compares the first rectified divided voltage P2 inputted into the input terminal IN-A with a preset first comparison voltage 43. The second comparator 42 compares the second rectified divided voltage P3 inputted into the input terminal IN-B with a preset second comparison voltage 44.

The input terminal IN-A of the first comparator 41 into which the first rectified divided voltage P2 is inputted is an inverting input terminal. The input terminal IN-B of the second comparator 42 into which the second rectified divided voltage P3 is inputted is a non-inverting input terminal. Therefore, the polarity of an output signal that is outputted from the first comparator 41 when the first rectified divided voltage P2 exceeds the first comparison voltage 43 is opposite to the polarity of an output signal that is outputted from the second comparator 42 when the second rectified divided voltage P3 exceeds the second comparison voltage 44. Specifically, the first comparator 41 is configured in such a manner that the output of the output terminal OUT-A goes Low when the first rectified divided voltage P2 inputted into the input terminal IN-A exceeds the first comparison voltage 43, and goes High when the first rectified divided voltage P2 drops below the first comparison voltage 43. The second comparator 42 is configured in such a manner that the output of the output terminal OUT-B goes High when the second rectified divided voltage P3 inputted into the input terminal IN-B exceeds the second comparison voltage 44, and goes Low when the second rectified divided voltage P3 drops below the second comparison voltage 44. Moreover, the output terminal OUT-A of the first comparator 41 and the output terminal OUT-B of the second comparator 42 are connected to each other at a connection point 45.

The switching circuit 5 outputs voltage information in relation to the voltage state of the alternating current power, as a pulse signal, on the basis of the output signal outputted from the first comparator 41 of the divided voltage comparator circuit 4, and the output signal outputted from the second comparator 42. The connection point 45 between the output terminal OUT-A of the first comparator 41 and the output terminal OUT-B of the second comparator 42 is connected to an input terminal 53 of the switching circuit 5.

The switching circuit 5 includes an isolation device that can isolate between the divided voltage comparator circuit 4 side and the computing device 6 side. The isolation device is, for example, a photocoupler including a light emitting diode 51 and a phototransistor 52. In the light emitting diode 51, the anode is connected to the input terminal 53 of the switching circuit 5, and the cathode is connected to a terminal 54 electrically continuous with the ground GND1. The phototransistor 52 is provided in such a manner as to face the light emitting diode 51. In the phototransistor 52, the collector is connected to an output terminal 55 of the switching circuit 5, and the emitter is connected to a terminal 56 electrically continuous with a ground GND2. Moreover, the input terminal 53 of the switching circuit 5 is connected to a power supply V1 via a resistor 57, and also connected to the ground GND1 via a resistor 58. On the other hand, the output terminal 55 is connected to a power supply V2 via a resistor 59. The ground GND1 to which a GND terminal 46 of the divided voltage comparator circuit 4 and the cathode of the light emitting diode 51 in the switching circuit 5 are connected, and the ground GND2 to which the emitter of the phototransistor 52 in the switching circuit 5 is connected are configured to be isolated GNDs between which electrical current does not flow.

The switching circuit 5 converts electrical signals outputted from the first comparator 41 and the second comparator 42 into light by the light emitting diode 51, receives the light by the phototransistor 52, and converts the light back into electrical signals. In this manner, the switching circuit 5 transfers signals, providing electrical isolation between the divided voltage comparator circuit 4 side and the computing device 6 side. In the switching circuit 5, the light emitting diode 51 turns on when the input terminal 53 is High, whereas the light emitting diode 51 turns off when the input terminal 53 is Low. When the light emitting diode 51 turns on, the phototransistor 52 turns on, and a Low signal is outputted from the output terminal 55 of the switching circuit 5. Moreover, when the light emitting diode 51 turns off, the phototransistor 52 turns off, and a High signal is outputted from the output terminal 55 of the switching circuit 5.

The computing device 6 determines the voltage state of the alternating current power on the basis of the output signal outputted from the output terminal 55 of the switching circuit 5. The computing device 6 detects the rising edge or falling edge of the output signal outputted from the output terminal 55. The computing device 6 measures the frequency (pulse interval) of the output signal (pulse signal) that transitions to High or Low on the basis of the rising edge or falling edge of the output signal. Moreover, the computing device 6 measures the pulse width of a High or Low pulse of the output signal. The computing device 6 determines the voltage state of the alternating current power on the basis of the measured frequency of the pulse signal, or pulse width of the output signal. The computing device 6 includes, for example, a microprocessor, an ASIC (Application Specific Integrated Circuit), or an FPGA (Field Programmable Gate Array).

Next, the operation of the input power monitoring circuit 1 in each voltage state of the alternating current power is described with reference to FIGS. 2 to 6 . In the embodiment, a case where the alternating current power is 200 V mains electric power is described below.

FIG. 2 is a diagram for explaining the operation of the input power monitoring circuit 1 of when the voltage of the alternating current power is a standard voltage, AC 200 V, that does not change. When the voltage of the alternating current power does not change from AC 200 V, the waveform peak value of a rectified voltage P1A of a pulsating current full wave rectified in the rectifier circuit 2 is 200×√2=282.8 Vp. The waveform illustrated in the top half of FIG. 2 is the waveform of a second rectified divided voltage P3A obtained by dividing the rectified voltage P1A according to the resistance of the resistors. The waveform of the second rectified divided voltage P3A is inputted into the input terminal IN-B of the second comparator 42 of the divided voltage comparator circuit 4. The waveform illustrated in the bottom half of FIG. 2 is a pulse signal waveform Q1 outputted to the output terminal 55 of the switching circuit 5.

When, as illustrated in FIG. 2 , the voltage value of the second rectified divided voltage P3A inputted into the input terminal IN-B exceeds the preset second comparison voltage 44 (refer to FIG. 1 ) (reaches, for example, a voltage value at a rectified voltage dividing point 71 of the second rectified divided voltage P3A), the output of the output terminal OUT-B of the second comparator 42 goes High. On the other hand, in terms of the first comparator 41, the voltage value of a first rectified divided voltage P2A to be inputted into the input terminal IN-A is set in such a manner as not to exceed the first comparison voltage 43 when the voltage of the alternating current power does not change from AC 200 V. Hence, the output of the output terminal OUT-A of the first comparator 41 is always in the High state when the voltage of the alternating current power is AC 200 V. Therefore, both of the output of the output terminal OUT-A and the output of the output terminal OUT-B go High at the voltage value of the rectified voltage dividing point 71 in FIG. 2 . Hence, the connection point 45 between the output terminals OUT-A and OUT-B goes High. Consequently, the light emitting diode 51 of the switching circuit 5 turns on, the phototransistor 52 turns on, and the pulse signal waveform Q1 to be outputted from the output terminal 55 of the switching circuit 5 goes Low.

Moreover, when the voltage value of the second rectified divided voltage P3A inputted into the input terminal IN-B becomes lower than the preset second comparison voltage 44 (drops below, for example, the voltage value of a rectified voltage dividing point 72 of the second rectified divided voltage P3A), the output of the output terminal OUT-B of the second comparator 42 goes Low. On the other hand, the output of the output terminal OUT-A of the first comparator 41 is always High as mentioned above. Therefore, the output of the output terminal OUT-B goes Low at the voltage value of the rectified voltage dividing point 72 in FIG. 2 . Therefore, the connection point 45 between the output terminals OUT-A and OUT-B goes Low. Consequently, the light emitting diode 51 of the switching circuit 5 turns off, the phototransistor 52 turns off, and the pulse signal waveform Q1 to be outputted from the output terminal 55 of the switching circuit 5 transitions from Low to High.

In this manner, when the voltage of the alternating current power does not change, the pulse signal waveform Q1 to be outputted from the switching circuit 5 transitions to the High or Low state according to the output state of the output terminal OUT-B of the second comparator 42. The frequency of the pulse signal waveform Q1 is based on the rectified voltage P1 of the pulsating current generated by full wave rectification, and therefore becomes 120 Hz. The High-and-Low duty cycle at this point in time is set to be approximately 50%.

FIG. 3 is a diagram for explaining the operation of the input power monitoring circuit 1 of when the voltage of the alternating current power drops to AC 150 V. When the voltage of the alternating current power drops to AC 150 V, the waveform peak value of a rectified voltage P1B of a pulsating current full wave rectified in the rectifier circuit 2 is 150×2=212.1 Vp.

As illustrated in FIG. 3 , the waveform peak value of the second rectified divided voltage P3B becomes lower than the waveform peak value of the second rectified divided voltage P3A (refer to FIG. 2 ) according to a drop in the voltage of the alternating current power (a drop from AC 200 V to AC 150 V). When the voltage value of the second rectified divided voltage P3B inputted into the input terminal IN-B exceeds the preset second comparison voltage 44 (reaches, for example, a voltage value at a rectified voltage dividing point 73 of the second rectified divided voltage P3B), the output of the output terminal OUT-B of the second comparator 42 goes High. On the other hand, the voltage value of a first rectified divided voltage P2B inputted into the input terminal IN-A of the first comparator 41 does not exceed the first comparison voltage 43 also when the voltage of the alternating current power drops from AC 200 V to AC 150 V. Hence, the output of the output terminal OUT-A of the first comparator 41 is always in the High state also when the voltage of the alternating current power is AC 150 V. Therefore, both of the output of the output terminal OUT-A and the output of the output terminal OUT-B go High at the voltage value of the rectified voltage dividing point 73 in FIG. 3 . Hence, the connection point 45 between the output terminals OUT-A and OUT-B goes High. Consequently, the light emitting diode 51 of the switching circuit 5 turns on, the phototransistor 52 turns on, and the pulse signal waveform Q2 to be outputted from the output terminal 55 of the switching circuit 5 goes Low.

Moreover, when the voltage value of the second rectified divided voltage P3B inputted into the input terminal IN-B becomes lower than the preset second comparison voltage 44 (drops below, for example, a voltage value at a rectified voltage dividing point 74 of the second rectified divided voltage P3B), the output of the output terminal OUT-B of the second comparator 42 goes Low. On the other hand, the output of the output terminal OUT-A of the first comparator 41 is always High as mentioned above. Therefore, the output of the output terminal OUT-B goes Low at the voltage value of the rectified voltage dividing point 74 in FIG. 3 . Therefore, the connection point 45 between the output terminals OUT-A and OUT-B goes Low. Consequently, the light emitting diode 51 of the switching circuit 5 turns off, the phototransistor 52 turns off, and the pulse signal waveform Q2 to be outputted from the output terminal 55 of the switching circuit 5 transitions from Low to High.

In this manner, when the voltage of the alternating current power drops to AC 150 V, the pulse signal waveform Q2 to be outputted from the switching circuit 5 transitions to the High or Low state according to the output state of the output terminal OUT-B of the second comparator 42. The frequency of the pulse signal waveform Q2 becomes 120 Hz as in the frequency of the pulse signal waveform Q1. The High period is longer in the High-and-Low duty cycle at this point in time than in the duty cycle described in FIG. 2 .

FIG. 4 is a diagram for explaining the operation of the input power monitoring circuit 1 of when the voltage of the alternating current power drops below AC 135 V. When the voltage of the alternating current power drops to AC 135 V, the waveform peak value of a rectified voltage P1C of a pulsating current full wave rectified in the rectifier circuit 2 is 135×2=190.9 Vp.

As illustrated in FIG. 4 , the waveform peak value of the second rectified divided voltage P3C becomes lower than the waveform peak value of the second rectified divided voltage P3A (refer to FIG. 2 ) according to a drop in the voltage of the alternating current power (a drop from AC 200 V to AC 135 V). When the voltage of the alternating current power drops to AC 135 V, the voltage value of the second rectified divided voltage P3C inputted into the input terminal IN-B of the second comparator 42 does not exceed the preset second comparison voltage 44. Hence, the output of the output terminal OUT-B of the second comparator 42 is always in the Low state. On the other hand, the voltage value of a first rectified divided voltage P2C inputted into the input terminal IN-A of the first comparator 41 does not exceed the first comparison voltage 43 also when the voltage of the alternating current power drops from AC 200 V to AC 135 V. Hence, the output of the output terminal OUT-A of the first comparator 41 is always in the High state also when the voltage of the alternating current power is AC 135 V. Therefore, the output of the output terminal OUT-B is always Low when the voltage of the alternating current power drops to AC 135 V. Hence, the connection point 45 between the output terminals OUT-A and OUT-B is always Low. Consequently, the light emitting diode 51 of the switching circuit 5 turns off, the phototransistor 52 turns off, and the pulse signal waveform Q3 to be outputted from the output terminal 55 of the switching circuit 5 is always High.

In this manner, when the voltage of the alternating current power drops below AC 135 V, the pulse signal waveform Q3 to be outputted from the switching circuit 5 is always in the High state according to the output state of the output terminal OUT-B of the second comparator 42.

As illustrated in FIGS. 2 to 4 , when the voltage (AC 200V) of the alternating current power does not change, or drops, the output of the output terminal OUT-A of the first comparator 41 does not change, and the output of the switching circuit 5 changes according to the output state of the output terminal OUT-B of the second comparator 42. Therefore, when the voltage of the alternating current power does not change, or drops, the voltage drop state can be detected by detecting the High or Low period of the output signal from the output terminal OUT-B of the second comparator 42.

Next, the operation of the input power monitoring circuit 1 in a case where the voltage (AC 200 V) of the alternating current power rises is described.

FIG. 5 is a diagram for explaining the operation of the input power monitoring circuit 1 of when the voltage of the alternating current power rises to AC 264 V. When the voltage of the alternating current power rises to AC 264 V, the waveform peak value of a rectified voltage P1D of a pulsating current full wave rectified in the rectifier circuit 2 is 264×2=373.3 Vp. The waveform of a second rectified divided voltage P3D and a pulse signal waveform Q4 in FIG. 5 are similar waveforms to the waveform of the second rectified divided voltage P3A and the pulse signal waveform Q1, which have been described in FIG. 2 .

As illustrated in FIG. 5 , the waveform peak value of the second rectified divided voltage P3D becomes higher than the waveform peak value of the second rectified divided voltage P3A (refer to FIG. 2 ) according to a rise in the voltage of the alternating current power (a rise from AC 200 V to AC 264 V). When the voltage value of the second rectified divided voltage P3D inputted into the input terminal IN-B exceeds the preset second comparison voltage 44 (reaches, for example, a voltage value at a rectified voltage dividing point 75 of the second rectified divided voltage P3D), the output of the output terminal OUT-B of the second comparator 42 goes High. On the other hand, the waveform peak value of a first rectified divided voltage P2D becomes higher than the waveform peak value of the first rectified divided voltage P2A according to a rise in the voltage of the alternating current power (a rise from AC 200 V to AC 264 V). Hence, the voltage value of the first rectified divided voltage P2D to be inputted into the input terminal IN-A of the first comparator 41 can be a voltage value exceeding the first comparison voltage 43 when the voltage of the alternating current power rises from AC 200 V to AC 264 V.

In terms of the waveform peak value of the rectified voltage P1 of the pulsating current full wave rectified in the rectifier circuit 2 varies between odd-numbered waveform peak values and even-numbered waveform peak values due to variations in the elements, such as the diodes D1 to D4, in the rectifier circuit 2. Consequently, there also arise similar variations in the first rectified divided voltage P2 and the second rectified divided voltage P3, which are generated by dividing the rectified voltage P1 according to the resistance of the resistors. In the example illustrated in FIG. 5 , a description is given of a case where variations occur in such a manner that the waveform peak values of the odd-numbered (2m+1) first rectified divided voltage P2D and second rectified divided voltage P3D are higher than the waveform peak values of the even-numbered (2m) first rectified divided voltage P2D and second rectified divided voltage P3D.

If such variations occur, the voltage value of the even-numbered (2m) first rectified divided voltage P2D inputted into the input terminal IN-A of the first comparator 41 does not exceed the first comparison voltage 43 even when the voltage of the alternating current power rises from AC 200 V to AC 264 V. On the other hand, a case may arise in which the voltage value of the odd-numbered (2m+1) first rectified divided voltage P2D exceeds the first comparison voltage 43.

Hence, when the even-numbered (2m) first rectified divided voltage P2D is inputted into the input terminal IN-A of the first comparator 41, the output of the output terminal OUT-A of the first comparator 41 is always in the High state also at AC 264 V. Therefore, both of the output of the output terminal OUT-A and the output of the output terminal OUT-B go High at the voltage value of the rectified voltage dividing point 75 in FIG. 5 . As a result, the connection point 45 between the output terminals OUT-A and OUT-B goes High. Consequently, the light emitting diode 51 of the switching circuit 5 turns on, the phototransistor 52 turns on, and the pulse signal waveform Q4 to be outputted from the output terminal 55 of the switching circuit 5 goes Low.

Moreover, when the voltage value of the second rectified divided voltage P3D inputted into the input terminal IN-B becomes lower than the preset second comparison voltage 44 (drops below, for example, a voltage value at a rectified voltage dividing point 76 of the second rectified divided voltage P3D), the output of the output terminal OUT-B of the second comparator 42 goes Low. On the other hand, when the even-numbered (2m) first rectified divided voltage P2D is inputted into the input terminal IN-A, the output of the output terminal OUT-A of the first comparator 41 is always High as mentioned above. Therefore, the output of the output terminal OUT-B is Low at the voltage value of the rectified voltage dividing point 76 in FIG. 5 . Therefore, the connection point 45 between the output terminals OUT-A and OUT-B goes Low. Consequently, the light emitting diode 51 of the switching circuit 5 turns off, the phototransistor 52 turns off, and the pulse signal waveform Q4 to be outputted from the output terminal 55 of the switching circuit 5 transitions from Low to High.

However, if variations occur as described above, when the odd-numbered (2m+1) first rectified divided voltage P2D and second rectified divided voltage P3D are inputted into the first comparator 41 and the second comparator 42, the following operation is performed.

The operation of the second comparator 42 is similar to the operation in the case where the even-numbered (2m) second rectified divided voltage P3D is inputted. On the other hand, when the odd-numbered (2m+1) first rectified divided voltage P2D is inputted into the input terminal IN-A of the first comparator 41, the waveform peak value of the odd-numbered (2m+1) first rectified divided voltage P2D is higher than the waveform peak value of the even-numbered (2m) first rectified divided voltage P2D. Therefore, the voltage value of the odd-numbered (2m+1) first rectified divided voltage P2D near the peak voltage is a voltage value exceeding the first comparison voltage 43. Hence, when the odd-numbered (2m+1) first rectified divided voltage P2D is inputted into the input terminal IN-A, the output of the output terminal OUT-A of the first comparator 41 enters the Low state near the peak voltage of the first rectified divided voltage P2D. Therefore, near the peak voltage of the odd-numbered (2m+1) second rectified divided voltage P3D in FIG. 5 , the output of the output terminal OUT-B of the second comparator 42 goes High, and the output of the output terminal OUT-A goes Low. Hence, the connection point 45 between the output terminals OUT-A and OUT-B goes Low. Consequently, the light emitting diode 51 of the switching circuit 5 turns off, the phototransistor 52 turns off, and the pulse signal waveform Q4 to be outputted from the output terminal 55 of the switching circuit 5 transitions to the High state.

In this manner, if the voltage of the alternating current power rises to AC 264 V, when the even-numbered (2m) rectified divided voltages P2D and P3D are inputted into the divided voltage comparator circuit 4, the pulse signal waveform Q4 to be outputted from the switching circuit 5 transitions to the High or Low state according to the output state of the output terminal OUT-B of the second comparator 42. When the odd-numbered (2m+1) rectified divided voltages P2D and P3D are inputted into the divided voltage comparator circuit 4, a transition from High to Low, or from Low to High, in accordance with the output state of the output terminal OUT-A of the first comparator 41 is added to the pulse signal waveform Q4 near the peak voltages of the rectified divided voltages P2D and P3D. Pulse waveforms of the odd-numbered (2m+1) rectified divided voltages P2D and P3D are added to a pulse waveform based on the rectified voltage P1 of the pulsating current generated by full wave rectification so that the frequency of the pulse signal waveform Q4 becomes 180 Hz.

FIG. 6 is a diagram for explaining the operation of the input power monitoring circuit 1 of when the voltage of the alternating current power rises to AC 275 V. When the voltage of the alternating current power rises to AC 275 V, the waveform peak value of a rectified voltage P1E of a pulsating current full wave rectified in the rectifier circuit 2 is 275×2=388.9 Vp. The waveform of a second rectified divided voltage P3E and a pulse signal waveform Q5 in FIG. 6 are similar waveforms to the waveform of the second rectified divided voltage P3A and the pulse signal waveform Q1, which have been described in FIG. 2 .

As illustrated in FIG. 6 , the waveform peak value of the second rectified divided voltage P3E becomes still higher than the waveform peak value of the second rectified divided voltage P3A (refer to FIG. 2 ) according to a rise in the voltage of the alternating current power (a rise from AC 200 V to AC 275 V). The operation of the second comparator 42 of when the voltage of the alternating current power rises to AC 275 V is similar to the operation of the second comparator 42 of when the voltage of the alternating current power rises to AC 264 V, which has been described in FIG. 5 .

On the other hand, the operation of the first comparator 41 of when the voltage of the alternating current power rises to AC 275 V includes the operation of the first comparator 41 of when the voltage of the alternating current power rises to AC 264 V, which has been described in FIG. 5 . Furthermore, also when an even-numbered (2m) first rectified divided voltage P2E (illustration omitted) is inputted into the input terminal IN-A of the first comparator 41, the voltage value of the first rectified divided voltage P2E near the peak voltage exceeds the first comparison voltage 43, and the output of the output terminal OUT-A enters the Low state. In other words, in the first comparator 41 of when the voltage of the alternating current power rises to AC 275 V, the output of the output terminal OUT-A enters the Low state at the voltage value of each first rectified divided voltage P2E near the peak voltage when the even-numbered (2m) first rectified divided voltage P2E is inputted into the input terminal IN-A, and when the odd-numbered (2m+1) first rectified divided voltage P2E is inputted.

Therefore, near the peak voltages of the even-numbered (2m) and odd-numbered (2m+1) second rectified divided voltages P3E in FIG. 6 , the output of the output terminal OUT-B of the second comparator 42 goes High, the output of the output terminal OUT-A of the first comparator 41 goes Low, and the connection point 45 between the output terminals OUT-A and OUT-B goes Low. Consequently, the light emitting diode 51 of the switching circuit 5 turns off, the phototransistor 52 turns off, and the pulse signal waveform Q5 to be outputted from the output terminal 55 of the switching circuit 5 enters the High state.

In this manner, if the voltage of the alternating current power rises to AC 275 V, when each rectified divided voltage P2D/P3D is inputted into the divided voltage comparator circuit 4, the pulse signal waveform Q5 to be outputted from the switching circuit 5 becomes a pulse signal to which a transition to High or Low in accordance with the output state of the output terminal OUT-A of the first comparator 41 is added near the peak voltage of the rectified divided voltage P2D/P3D. A pulse waveform of each of the (even-numbered and odd-numbered) rectified divided voltages P2D/P3D is added to the pulse waveform based on the rectified voltage P1 of the pulsating current generated by full wave rectification so that the frequency of the pulse signal waveform Q5 becomes 240 Hz.

As illustrated in FIGS. 5 and 6 , when the voltage (AC 200 V) of the alternating current power rises, the output state of the output terminal OUT-A of the first comparator 41 changes, and a pulse waveform associated with the change of the output state appears in a pulse signal waveform Qn to be outputted from the switching circuit 5. Therefore, when the voltage of the alternating current power rises, a voltage rise state can be detected by measuring the frequency (pulse interval) of the pulse signal waveform Qn.

Next, the operation of determining the voltage state of the alternating current power by the computing device 6 is described with reference to FIG. 7 .

When a pulse signal is inputted from the output terminal 55 of the switching circuit 5 into the computing device 6, the computing device 6 detects the rising edge of the pulse signal that has been inputted, and measures the High period of the pulse signal. The computing device 6 determines whether or not the High period of the pulse signal has continued for more than a predetermined warning detection time (step S10).

If the High period of the pulse signal is not more than the warning detection time in step S10 (NO in step S10), the computing device 6 calculates the frequency of the pulse signal on the basis of the rising edge of the pulse signal (step S11).

On the other hand, if the High period of the pulse signal is more than the warning detection time in step S10 (YES in step S10), the computing device 6 sets a power supply voltage drop warning that warns a drop in the voltage of the alternating current power (step S12).

Following step S12, the computing device 6 determines whether or not the High period of the pulse signal has continued for more than a voltage drop alarm detection time (step S13).

If the High period of the pulse signal is more than the voltage drop alarm detection time in step S13 (YES in step S13), the computing device 6 sets a voltage drop alarm that issues an alarm for a drop in the voltage of the alternating current power (step S14), and then moves on to step S11.

On the other hand, if the High period of the pulse signal is not more than the voltage drop alarm detection time in step S13 (NO in step S13), the computing device 6 moves directly to step S11.

Following step S11, the computing device 6 determines whether or not the calculated frequency of the pulse signal (the calculated frequency) is equal to or less than 90 Hz (step S15). The pulse signal is detected on the basis of the rectified voltage P1 of the pulsating current generated from the full wave rectified voltage of the alternating current power. Hence, that the frequency of the pulse signal is equal to or less than 90 Hz indicates that the frequency of the alternating current power is equal to or less than 90/2=45 Hz. Therefore, if the alternating current power is AC 200 V, 50 Hz, the computing device 6 determines whether or not the frequency has dropped by 5 Hz or more from 50 Hz.

If the frequency of the pulse signal is equal to or less than 90 Hz in step S15 (YES in step S15), the computing device 6 sets a power supply frequency drop warning that warns a drop in the frequency of the alternating current power (step S16), and ends the determination process.

On the other hand, if the frequency of the pulse signal is not equal to or less than 90 Hz in step S15 (NO in step S15), the computing device 6 performs a moving-average process on the calculated frequency of the pulse signal (step S17).

Next, the computing device 6 determines whether or not the frequency of the pulse signal that has been obtained by the moving-average process (the detected frequency) is equal to or greater than 180 Hz, and also determines whether or not the frequency has remained at 180 Hz or greater for more than an overvoltage alarm detection time (step S18).

If the frequency has remained at 180 Hz or greater for more than the overvoltage alarm detection time in step S18 (YES in step S18), the computing device 6 sets an overvoltage alarm/warning that issues an alarm for a rise in the voltage of the alternating current power (step S19), and ends the determination process.

On the other hand, if the frequency has not remained at 180 Hz or greater for more than the overvoltage alarm detection time in step S18 (NO in step S18), the computing device 6 ends the determination process automatically. The computing device 6 moves on to a data protection process of storing in-process data in memory if the voltage drop alarm and the overvoltage alarm/warning are set after the end of the determination process.

As described above, the input power monitoring circuit 1 according to the embodiment includes: the rectifier circuit 2 configured to rectify periodic input power and generate the rectified voltage P1; the divided voltage generator circuit 3 configured to divide the rectified voltage P1 and generate the first rectified divided voltage P2 and the second rectified divided voltage P3 being a voltage lower than the first rectified divided voltage P2; the divided voltage comparator circuit 4 including the first comparator 41 configured to compare the first rectified divided voltage P2 with the first comparison voltage 43, and the second comparator 42 configured to compare the second rectified divided voltage P3 with the second comparison voltage 44; the switching circuit 5 configured to output a pulse signal in relation to the voltage state of the input power on the basis of an output signal outputted from the first comparator 41, and an output signal outputted from the second comparator 42; and the computing device 6 configured to determine the voltage state of the input power on the basis of the pulse signal outputted from the switching circuit 5. The divided voltage comparator circuit 4 (the first comparator 41 and the second comparator 42 in the divided voltage comparator circuit 4) is configured in such a manner that the polarity of the output signal that is outputted from the first comparator 41 when the first rectified divided voltage P2 exceeds the first comparison voltage 43 is opposite to the polarity of the output signal that is outputted from the second comparator 42 when the second rectified divided voltage P3 exceeds the second comparison voltage 44. Furthermore, the output terminal OUT-A of the first comparator 41 and the output terminal OUT-B of the second comparator 42 are connected to each other in the divided voltage comparator circuit 4. The connection point 45 between the output terminal OUT-A of the first comparator 41 and the output terminal OUT-B of the second comparator 42 is connected to the input terminal 53 of the switching circuit 5. The computing device 6 measures the frequency of the pulse signal, and determines the voltage state of the input power on the basis of the measured frequency. According to this configuration, a pulse signal is generated on the basis of the output signals outputted from the first comparator 41 and the second comparator 42. The voltage state of the input power is determined on the basis of the pulse width and frequency of the generated pulse signal. Consequently, if the input power voltage drops, the voltage state can be determined on the basis of the pulse width of the pulse signal. Hence, during a power failure, the pulse signal is always in the High state. Therefore, a wrong determination on the detection of a power failure can be prevented. Moreover, if the input power voltage rises, the voltage state can be determined on the basis of the frequency of the pulse signal. Hence, a wrong determination associated with a change in pulse width caused by voltage distortion can be restrained. Therefore, the voltage state can be determined excellently.

Moreover, according to the input power monitoring circuit 1, the first comparator 41 outputs Low when the first rectified divided voltage P2 exceeds the first comparison voltage 43, and outputs High when the first rectified divided voltage P2 drops below the first comparison voltage 43. Moreover, the second comparator 42 outputs High when the second rectified divided voltage P3 exceeds the second comparison voltage 44, and outputs Low when the second rectified divided voltage P3 drops below the second comparison voltage 44. The first comparator 41 and the second comparator 42 are set in such a manner as to be brought into such output states. As a result, the voltage state of the input power can be determined appropriately on the basis of a single signal outputted from the switching circuit 5 by connecting the output terminal OUT-A of the first comparator 41 and the output terminal OUT-B of the second comparator 42.

Moreover, according to the input power monitoring circuit 1, the first comparator 41 is configured in such a manner that the first rectified divided voltage P2 does not exceed the first comparison voltage 43 at least when the input power voltage drops. The first comparator 41 is set in such a manner as to be brought into such an output state. As a result, the voltage state of the input power can be determined appropriately on the basis of a single signal outputted from the switching circuit 5 by connecting the output terminal OUT-A of the first comparator 41 and the output terminal OUT-B of the second comparator 42.

Moreover, according to the input power monitoring circuit 1, the computing device 6 detects only a High period or a Low period of the output signal outputted from the second comparator 42, to determine the voltage state of the input power. The rectified divided voltage and the comparison voltage are set in such a manner that only the output signal that is outputted from the second comparator 42 at a normal voltage level of the input power transitions to the Low state. As a result, a voltage anomaly (voltage drop) in the input power can be determined simply by monitoring the output signal of the second comparator 42.

Moreover, according to the input power monitoring circuit 1, the computing device 6 notifies a voltage anomaly in the input power to, for example, a worker when the frequency of the pulse signal outputted from the switching circuit 5 exceeds a predetermined threshold. Consequently, a voltage anomaly (voltage rise) in the input power can be determined, and also the occurrence of the voltage anomaly can be notified to the worker.

Moreover, according to the input power monitoring circuit 1, the computing device 6 determines that the input power voltage has dropped when the output from the switching circuit 5 is always High. Also when the input power voltage is a direct-current voltage with no periodicity, a drop in the input voltage can be detected by use of the fact that the output of the switching circuit 5 is always at High level during a voltage drop in the input power.

Moreover, according to the input power monitoring circuit 1, the switching circuit 5 includes the isolation device capable of isolating between the divided voltage comparator circuit 4 side and the computing device 6 side. Hence, the influence of a change in the input power voltage on the computing process of the computing device 6 can be restrained.

Up to this point the embodiment of the present disclosure has been described. In terms of this, it is needless to say that the technical scope of the present disclosure should not be construed in a limited manner by the description of the embodiment. The embodiment is a mere example. Those skilled in the art understand that the embodiment can be modified in various manners within the technical scope of the present disclosure described in the claims. The technical scope of the present disclosure should be determined on the basis of the scope described in the claims and the scope of equivalents thereof.

The foregoing detailed description has been presented for the purposes of illustration and description. Many modifications and variations are possible in light of the above teaching. It is not intended to be exhaustive or to limit the subject matter described herein to the precise form disclosed. Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims appended hereto. 

What is claimed is:
 1. An input power monitoring circuit comprising: a rectifier circuit configured to rectify periodic input power and generate a rectified voltage; a divided voltage generator circuit configured to divide the rectified voltage and generate a first rectified divided voltage and a second rectified divided voltage being a voltage lower than the first rectified divided voltage; a divided voltage comparator circuit including a first comparator configured to compare the first rectified divided voltage with a first comparison voltage, and a second comparator configured to compare the second rectified divided voltage with a second comparison voltage; a switching circuit configured to output a pulse signal in relation to a voltage state of the input power based on an output signal outputted from the first comparator, and an output signal outputted from the second comparator; and a computing device configured to determine the voltage state of the input power based on the pulse signal, wherein the divided voltage comparator circuit is configured in such a manner that polarity of the output signal that is outputted from the first comparator upon the first rectified divided voltage exceeding the first comparison voltage is opposite to polarity of the output signal that is outputted from the second comparator upon the second rectified divided voltage exceeding the second comparison voltage, an output terminal of the first comparator and an output terminal of the second comparator are connected to each other in the divided voltage comparator circuit, a connection point between the output terminal of the first comparator and the output terminal of the second comparator is connected to an input terminal of the switching circuit, and the computing device measures frequency of the pulse signal, and determines the voltage state of the input power based on the measured frequency.
 2. The input power monitoring circuit according to claim 1, wherein the first comparator outputs Low upon the first rectified divided voltage exceeding the first comparison voltage, and outputs High upon the first rectified divided voltage dropping below the first comparison voltage, and the second comparator outputs High upon the second rectified divided voltage exceeding the second comparison voltage, and outputs Low upon the second rectified divided voltage dropping below the second comparison voltage.
 3. The input power monitoring circuit according to claim 2, wherein the first comparator is configured in such a manner that the first rectified divided voltage does not exceed the first comparison voltage at least upon the input power voltage dropping.
 4. The input power monitoring circuit according to claim 1, wherein the computing device detects only a High period or a Low period of the output signal outputted from the second comparator to determine the voltage state of the input power.
 5. The input power monitoring circuit according to claim 1, wherein the computing device notifies a voltage anomaly in the input power upon the frequency of the pulse signal exceeding a predetermined threshold.
 6. The input power monitoring circuit according to claim 2, wherein the computing device notifies a voltage anomaly in the input power upon the frequency of the pulse signal exceeding a predetermined threshold.
 7. The input power monitoring circuit according to claim 3, wherein the computing device notifies a voltage anomaly in the input power upon the frequency of the pulse signal exceeding a predetermined threshold.
 8. The input power monitoring circuit according to claim 1, wherein the computing device determines that the input power voltage has dropped upon an output from the switching circuit being always High.
 9. The input power monitoring circuit according to claim 2, wherein the computing device determines that the input power voltage has dropped upon an output from the switching circuit being always High.
 10. The input power monitoring circuit according to claim 3, wherein the computing device determines that the input power voltage has dropped upon an output from the switching circuit being always High.
 11. The input power monitoring circuit according to claim 1, wherein the switching circuit includes an isolation device capable of isolating between the divided voltage comparator circuit side and the computing device side. 